1. Technical Field
The invention disclosed broadly relates to bus communication systems and more particularly relates to the arbitration of control of the bus by contending devices desiring access to a common bus for the transfer of data.
2. Background Art
In high speed communication systems having a common bus interconnected to multiple communicating modules, latency due to arbitration of contending modules and message transfer is a serious problem. When a plurality of communicating modules vie for a common data bus simultaneously, an arbitration code is necessary to prioritize the requesting modules to select the module to receive access to the bus.
A bus acquisition system is disclosed in U.S. Pat. No. 4,736,366 to Rickard and a bus transceiver is disclosed in U.S. Pat. No. 4,756,006 to Rickard, both patents owned by the common assignee of this invention. The teachings of these two patents are herein incorporated by reference.
A typical communication system may have up to 32 communicating modules which compete for a common bus. One hundred twenty-eight logical priority levels can be ascribed to the 32 modules. The arbitration sequence, which takes place upon the data bus, requires eight bus cycles to resolve the winner's logical and physical ID. There are times when only one module is in contention for the bus. Even though it is common for only one module to be vying for the bus at any given time, that module must suffer a full eight-cycle latency of arbitration sequence.
A better technique to achieve low latency arbitration would be to add two cycles at the beginning of the arbitration sequence to determine if one or more modules are contending for control of the bus. If only one module is contending for the bus, it is not necessary to continue to the eight-cycle arbitration sequence, but give that module immediate access to the bus.